Current Issue : July - September Volume : 2014 Issue Number : 3 Articles : 4 Articles
Proliferation ofmutually exclusive applications on circuits and the higher cost of silicon make the resource sharing more and more\nimportant.Thestate-of-the-art synthesis toolsmay often be unsatisfactory. Their efficiencymay depend on the hardware description\nstyle.Nevertheless, today, different applications in a circuit can be developed by different developers. This paper proposes an efficient\nmethod to improve resource sharing between mutually exclusive applications with no dependence on the coding style. It takes the\nadvantage of the possibility of resource sharing as done in FPGA and of predefined multiple functions as in ASIC....
Distance-Ranked Fault Identification (DRFI) is a dynamic reconfiguration technique which employs runtime inputs to conduct\nonline functional testing of fielded FPGA logic and interconnect resources without test vectors. At design time, a diverse set\nof functionally identical bitstream configurations are created which utilize alternate hardware resources in the FPGA fabric. An\nordering is imposed on the configuration pool as updated by the PageRank indexing precedence.The configurations which utilize\npermanently damaged resources and hence manifest discrepant outputs, receive lower rank are thus less preferred for instantiation\non the FPGA. Results indicate accurate identification of fault-free configurations in a pool of pregenerated bitstreams with a low\nnumber of reconfigurations and input evaluations. For MCNC benchmark circuits, the observed reduction in input evaluations\nis up to 75% when comparing the DRFI technique to unguided evaluation. The DRFI diagnosis method is seen to isolate all 14\nhealthy configurations froma pool of 100 pregenerated configurations, and thereby offering a 100% isolation accuracy provided the\nfault-free configurations exist in the design pool. When a complete recovery is not feasible, graceful degradation may be realized\nwhich is demonstrated by the PSNR improvement of images processed in a video encoder case study....
A variety of platforms, such as micro-unmanned vehicles, are limited in the amount of computational hardware they can support\ndue to weight and power constraints. An efficient stereo vision algorithm implemented on an FPGA would be able to minimize\npayload and power consumption in microunmanned vehicles, while providing 3D information and still leaving computational\nresources available for other processing tasks. This work presents a hardware design of the efficient profile shape matching stereo\nvision algorithm. Hardware resource usage is presented for the targeted micro-UV platform, Helio-copter, that uses the Xilinx\nVirtex 4 FX60 FPGA. Less than a fifth of the resources on this FGPA were used to produce dense disparity maps for image sizes up\nto 450 Ã?â?? 375, with the ability to scale up easily by increasing BRAM usage. A comparison is given of accuracy, speed performance,\nand resource usage of a census transform-based stereo vision FPGA implementation by Jin et al. Results show that the profile shape\nmatching algorithm is an efficient real-time stereo vision algorithm for hardware implementation for resource limited systems such\nas microunmanned vehicles....
Self-adaptive systems need to monitor themselves, to check their internal behaviour and design assumptions about runtime inputs\nand conditions. This kind of monitoring for self-adaptive systems can include collecting statistics about such systems themselves\nwhich can be computationally intensive (for detailed statistics) and hence time consuming, with possible negative impact on selfadaptive\nresponse time. To mitigate this limitation, we extend the technique of in-circuit runtime assertions to cover statistical\nassertions in hardware.The presented designs implement several statistical operators that can be exploited by self-adaptive systems;\na novel optimization is developed for reducing the number of pairwise operators from O(N) to O(log (N)). To illustrate the\npracticability and industrial relevance of our proposed approach,we evaluate our designs, chosen froma class of possible application\nscenarios, for their resource usage and the tradeoffs between hardware and software implementations....
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